1. Field of the Invention
The present invention relates generally to a contact structure and to a method of making an electric contact to a conductive layer during the manufacture of an integrated circuit. More particularly, the invention relates to a method of fabricating a contact during the manufacture of a merged dynamic random access memory (DRAM) and a logic circuit (the merged device being referred to as MDL).
2. Description of Related Art
Self-aligned contacts (SAC) for cell pads recently have become widely employed for making bit line contacts in DRAMs because the contact size has now been reduced to sub-half-micrometer levels. This has been due primarily to reduced design rules used to manufacture such devices. The prior art typically employed a method of forming a gate spacer by depositing a silicon nitride layer of about 1500 to 2000 xc3x85 on the gate electrode in order to obtain a shoulder between the cell contact pad and the gate electrode. It is well known in the prior art that this shoulder should preferably be more than 400 xc3x85. It is difficult, however, to apply such prior art teachings to the manufacture of a high-density DRAM or of an MDL chip.
The reason for this difficulty is the following. In the case of an MDL chip, it is desirable to form metal contacts on the gate electrodes of peripheral logic circuits simultaneously with the contact pads of the bit lines in the memory cell regions. It is further necessary, in this case, to remove the silicon nitride capping layer from the gate electrode in order to make the metal contact for the peripheral logic circuits, while at the same time maintaining an overlap margin between the cell contact pad and the bit line contact in the memory cell regions.
The details of the herein described technical problems of the prior art can be explained by reference to FIGS. 1 and 2. FIG. 1 is a schematic diagram illustrating a contact structure fabricated in a DRAM cell, and in a peripheral circuit or logic region, according to the prior art.
Referring now to FIG. 1, electrical connections are made to the conducting layer 114 through contacts 115, 116, and 117 on the contact pad 121 of the cell region and on the active region 111 and gate electrode 112 of the peripheral region, respectively. According to the prior art, an oxide flow is usually employed for forming an interlayer dielectric 113 and a gate electrode typically includes a stacked structure comprised of a doped polysilicon layer 118, a tungsten silicide layer 112, and a silicon nitride layer 119.
In FIG. 1, it can be seen that the vertical depth of the hole for contact 115 for the contact pad 121 in the cell region is different from the depth of the hole for 116 for the active region of the peripheral circuit. In addition, it can be seen that the depth of the hole for contact 117 for the gate electrode 112 also differs from the depth of the hole for contact 115 for the cell contact pad 121. Accordingly, one can not rule out the possibility that the surface of the active region 111 may be damaged due to excessive etching that may occur during the process of forming holes for contacts 115, 116, and 117.
Furthermore, the silicon nitride capping layer 119 should be etched after the removal of interlayer dielectric 113 when forming contact hole 117 on the gate electrode 112. This is especially important in the peripheral or logic circuit region of the integrated circuit. Therefore, any slight lithographic misalignment that may, inevitably, occur in defming contact hole 115 may result in an electric shortage between the gate tungsten silicide 131 and the active region 110 in the cell region (see, FIG. 2). The electric path of the above shortage is through contact pad 121 and contact hole 115.
FIG. 2 is a schematic diagram illustrating this electric shortage problem that may occur due to lithographic misalignment according to the prior art. The electric shortage between the gate electrode 131 (usually comprised of tungsten silicide) and the contact pad 121 via contact hole 115 in the cell region is frequently observed because the contact hole 115 in the cell region is formed simultaneously with contact hole 117 in the peripheral circuits. The electric shortage problem between the gate electrode 131 and the cell contact pad 121 occurs even more frequently when the minimum contact size is reduced to the order of a sub-half-micrometer, as is usually found in recent highly integrated circuits.
Accordingly, there exists a need to develop a contact and a method of making the contact that allows an overlap margin between the contact hole and the cell contact pad, even if lithographic misalignment occurs during manufacturing. There also exists a need to develop a contact and a method of making the contact that provides an improved metal contact on the gate electrode having a gate-capping layer.
It is therefore a feature of the present invention to satisfy these needs by providing a contact and a method of making the contact that allows an overlap margin between the contact hole and the cell contact pad, even during lithographic misalignment. It is an additional feature of the invention to provide a contact and a method of making the contact that provides improved metal contact on a gate electrode having a gate-capping layer.
In accordance with these and other features readily apparent to those skilled in the art, there is provided a semiconductor device having a cell region and a peripheral region, each region containing at least an active region, where the device includes: a first conductivity type field effect transistor (FET) that does not have a thermal oxide layer on a surface of an active region in the peripheral region; and a second conductivity type FET that contains a thermal oxide layer on a surface of an active region in the peripheral region.
In accordance with an additional feature of the invention, there is provided a method of making a semiconductor device comprising: providing a substrate that includes at least a cell region and a peripheral or logic region, each region having active and gate regions where the gate regions are to contain at least one gate structure; forming a plurality of gate structures on the substrate, each of the plurality of gate structures comprising at least a gate-capping layer and an oxide layer; forming a first mask layer, exposing said first mask layer in the peripheral region of the substrate, active and gate regions of a first conductivity type FET, and at least one gate region of a second conductivity type FET; implanting a first conductivity type impurity on the substrate covered with the first mask layer; removing the first mask layer; forming a second mask layer, and exposing said second mask layer in the peripheral region of the substrate, active and gate regions of a second conductivity type FET, and a gate region of a first conductivity type FET; implanting a second conductivity type impurity on the substrate covered with the second mask layer; and removing the gate-capping layer from the plurality of gate structures in the peripheral region.
It is an additional feature of the present invention to provide a method of making a semiconductor integrated circuit having a first circuit region and a second circuit region comprising: providing a substrate having at least a first circuit region and a second circuit region, each of the first and second circuit regions having active and gate regions, where the gate regions are to contain at least one gate structure; forming a plurality of gate structures in the first and second circuit regions, the gate structures comprising at least a gate-capping layer; forming a silicon oxide layer on the substrate including the plurality of gate structures for subsequent ion implantation; forming a first mask layer on the substrate; patterning the first mask layer to expose at least one gate structure of the first circuit region and at least one active region of a first conductivity type FET in the first circuit region; implanting impurities of a first conductivity type on the exposed surface of the substrate through the patterned first mask layer; eliminating the silicon oxide layer on the surface of the substrate; removing the first mask layer; forming a second mask layer; patterning the second mask layer to expose at least one gate structure of the first circuit region and at least one active region of a second conductivity type FET of the first circuit region; implanting impurities of a second conductivity type on the exposed surface of the substrate through the patterned second mask layer; eliminating the gate-capping layer on the gate structures in the first circuit region; removing the second mask layer; forming an interlayer dielectric film on the substrate; and forming contacts by exposing the surface of at least one active region of the first circuit region, the surface of at least one gate region of the first circuit region, and the surface of at least one active region of the second circuit region.